Generally, through-silicon vias (TSVs) are formed in a semiconductor wafer by initially forming an opening at least partially through a substrate. A barrier layer is formed to line the opening in order to prevent a later-formed conductive material (e.g., copper) from diffusing into the substrate, where it might deteriorate the overall performance of other devices formed on the semiconductor wafer. As such, this barrier layer prevents damage caused by the conductive material.
However, the barrier layer is typically formed through a physical vapor deposition (PVD) process, which generally has a poor step coverage. This poor step coverage results in the barrier layer having a smaller thickness at the bottom of the TSV opening along the sidewalls, and can induce a problem with the continuity of the barrier. Such a problem with continuity may result in gaps of coverage, which would not only allow conductive material to diffuse into the substrate, but may also cause problems during subsequent electroplating of conductive material into the opening.
One solution to this discontinuity is to simply continue the PVD barrier formation process until the continuity of the barrier layer in the TSV opening has been assured. However, this process also increases the thickness of the barrier layer on the surface of the substrate (outside of the TSV opening). This increase in thickness can cause variation problems after the barrier layer has been removed from the surface by a chemical mechanical polishing (CMP) process.